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MAX2104CCM Rev. A
RELIABILITY REPORT FOR MAX2104CCM PLASTIC ENCAPSULATED DEVICES
January 28, 2001
MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX2104 Successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information IV. .......Die Information V. ........Quality Assurance Information VI. .......Reliability Evaluation ......Attachments
I. Device Description A. General The MAX2104 low-cost direct-conversion tuner IC is designed for use in digital direct-broadcast satellite (DBS) television set-top box units. Its direct-conversion architecture reduces system cost compared to devices with IFbased architectures. The MAX2104 directly converts L-band signals to baseband signals using a broadband I/Q downconverter. The operating frequency range extends from 925MHz to 2175MHz. The IC includes an LNA gain control, I and Q downconverting mixers, lowpass filters with gain control and frequency control, a local oscillator (LO) buffer with a 90 quadrature network, and a charge-pump based PLL for frequency control. The MAX2104 also has an on-chip LO, requiring only an external varactor-tuned LC tank for operation. The output of the LO drives the internal quadrature generator and dual modulus prescaler. An on-chip crystal amplifier drives a reference divider as well as a buffer amplifier to drive off-chip circuitry. The MAX2104 is offered in a 48-pin TQFP-EP package.
B. Absolute Maximum Ratings Item Vcc to GND All other pins to GND RF1+ to RF1-, RF2+ to RF2-, TANK+ to TANK-, IDC+ to IDC-, QDC+ to QDCIOUT_,QOUT_ to GND Short Circuit Duration PSOU+, PSOUT- to GND Short Circuit Duration Continuous Current (any pin) Storage Temperature Range Lead Temperature (soldering, 10s) Junction Temperature Continuous Power Dissipation (TA = +70C) 48-Pin TQFP Derates above +70C 48-Pin TQFP Rating -0.5V to +7V -0.3V to (VCC + 0.3V) +/-2V 10s 10s 20mA -65C to +150C +300C +150C 1500mW 27mW/C
II. Manufacturing Information A. Description/Function: B. Process: Direct-Conversion Tuner IC for Digital DBS Application GST2 - High Speed Double Poly-Silicon Bipolar Process
C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: Oregon, USA Malaysia January, 1999
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: 48-Lead TQFP Copper Solder Plate Silver-filled Epoxy Gold (1.02mil dia.) Epoxy with silica filler Buildsheet # 05-7001-0319 Class UL94-V0
I. Classification of Moisture Sensitivity per JEDEC standard JESD22-A112: Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 96 x 96 Si3N4/SiO2 (Silicon nitride/ Silicon dioxide) Poly / Au None 2 microns (as drawn) 2 microns (as drawn) 5 mil. Sq. SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Reliability Lab Manager) Bryan Preeshl (Executive Director of QA) Kenneth Huening (Vice President) B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 150C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 (Chi square value for MTTF upper limit) 192 x 9823 x 50 x 2 Temperature Acceleration factor assuming an activation energy of 0.8eV = 9.70 x 10-9 = 9.70 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability qualification and monitor programs. Maxim also performs weekly Burn-In on samples from production to assure reliability of its processes. The reliability required for lots which receive a burn-in qualification is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on rejects from lots exceeding this level. Maxim also performs 1000 hour life test monitors quarterly for each process. This data is published in the Product Reliability Report (RR-1M) located on the Maxim website at http://www.maxim-ic.com . B. Moisture Resistance Tests Maxim evaluates pressure pot stress from every assembly process during qualification of each new design. Pressure Pot testing must pass a 20% LTPD for acceptance. Additionally, industry standard 85C/85%RH or HAST tests are performed quarterly per device/package family. C. E.S.D. and Latch-Up Testing The WR31 die type has been found to have all pins able to withstand a transient pulse of 1000V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 100mA and/or 20V.
Table 1 Reliability Evaluation Test Results MAX2104CCM
TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
Static Life Test (Note 1) Ta = 150C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
50
0
DC Parameters & functionality
77
0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters 77 0
Note 1: Life Test Data may represent plastic D.I.P. qualification lots. Note 2: Generic Process/Package Data
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc).
3.4 a.
Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1, or VCC2) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
b.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B
R = 1.5k C = 100pf
TERMINAL D Mil Std 883D Method 3015.7 Notice 8

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